SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A1A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PI_ADDR_SPACE | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_BIST_LFSR_PATTERN_DONE | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_BIST_RESULT | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_BIST_GO | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | PI_ADDR_SPACE | R/W | 0h | Sets the number of address bits to check during BIST operation. The end address of BIST is start_address+[1 shifted up by PI_ADDR_SPACE]-1. The end address should not beyond the actual memory address range. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_BIST_LFSR_PATTERN_DONE | R | 0h | BIST operation lfsr pattern, data pattern 1'b0 means the data is useful,1'b1 means next pattern sequence can ingore. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | PI_BIST_RESULT | R | 0h | BIST operation status [pass/fail]. Bit [0] indicates data check status and bit [1] indicates address check status. Value of 1 is a passing result. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_BIST_GO | R/W | 0h | Initiate a BIST operation. Set to 1 to trigger. Reset Source: ctl_amod_g_rst_n |