SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A3B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_WDQLVL_CL_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_NTP_TRAIN_EN_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_WDQLVL_EN_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_WDQLVL_VREF_DELTA_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | PI_WDQLVL_CL_F1 | R/W | 0h | CL when the Read DBI disabled while doing WDQ training for frequency set 1. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PI_NTP_TRAIN_EN_F1 | R/W | 0h | Indicates whether the no topology WDQ training is enabled. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Reset Source: ctl_amod_g_rst_n |
| 15:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | PI_WDQLVL_EN_F1 | R/W | 0h | Indicates if Write DQ leveling is enabled for frequency set 1. Bit[1] represents the support when non-initialization. Bit[0]represents the support when initialization. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | PI_WDQLVL_VREF_DELTA_F1 | R/W | 0h | The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 1. Reset Source: ctl_amod_g_rst_n |