SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A138h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_WDQLVL_NIBBLE_MODE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_SWLVL_SM2_DM_NIBBLE_START | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_TDFI_WDQLVL_WW | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_TDFI_WDQLVL_WW | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | PI_WDQLVL_NIBBLE_MODE | R/W | 0h | WDQ Training Nibble mode indication. When set to 1, nibble mode is enabled, and the training timing is doubled. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_SWLVL_SM2_DM_NIBBLE_START | W | 0h | Start command for stage 2, when in the process of DM leveling or nibble mode. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:10 | RESERVED | NONE | 0h | Reserved |
| 9:0 | PI_TDFI_WDQLVL_WW | R/W | 0h | Minimum number of DFI clocks to be inserted between write commands during the DM portion of write DQ training. Reset Source: ctl_amod_g_rst_n |