SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 862Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | AXI0_R_PRIORITY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | AXI0_FIXED_PORT_PRIORITY_ENABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | AXI0_ALL_STROBES_USED_ENABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TDQSCK_MIN_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | AXI0_R_PRIORITY | R/W | 0h | Priority of read commands from AXI port 0. 0 is the highest priority. This may only be changed before initialization begins or when the controller is quiescent, there is no data in the port FIFOs, and the AXI0_FIXED_PORT_PRIORITY_ENABLE parameter is low. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | AXI0_FIXED_PORT_PRIORITY_ENABLE | R/W | 0h | Defines the priority control for AXI port 0 as per-port or per-command. Set to 1 for per-port with priority defined through the AXI.0._R_PRIORITY and AXI.0._W_PRIORITY parameters. Clear to 0 for per-command. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | AXI0_ALL_STROBES_USED_ENABLE | R/W | 0h | Enables use of the AWALLSTRB signal for AXI port 0. Set to 1 to enable. Reset Source: ctl_amod_g_rst_n |
| 7:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | TDQSCK_MIN_F2 | R/W | 0h | Additional delay needed for tDQSCK. FC=2 Reset Source: ctl_amod_g_rst_n |