SPRUJ83 User guide | 德州仪器 TI.com.cn

SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1

14.8.6.3.2.13 DPHY_TX_WIZ_CONFIG_PLL_CTRL Register

3.2.13.1 DPHY_TX_WIZ_CONFIG_PLL_CTRL Register (Offset = 4h) [reset = 10FF0101h]

Sets the PLL info.

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Table 14-23337 Instance Table

Instance Name	Physical Address
DPHY_TX0	301C 0004h

Figure 14-11554 DPHY_TX_WIZ_CONFIG_PLL_CTRL Name Register

31	30	29	28	27	26	25	24
PLL_LOCK	PSO_DISABLE	PLL_PSO	PLL_PD	RESERVED		PLL_FBDIV
R	R/W	R/W	R/W	NONE		R/W
0h	0h	0h	1h	0h		FFh
23	22	21	20	19	18	17	16
PLL_FBDIV
R/W
FFh
15	14	13	12	11	10	9	8
RESERVED		PLL_OPDIV
NONE		R/W
0h		1h
7	6	5	4	3	2	1	0
RESERVED			PLL_IPDIV
NONE			R/W
0h			1h

Table 14-23338 DPHY_TX_WIZ_CONFIG_PLL_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
31	PLL_LOCK	R	0h	Signal to indicate that PLL has got locked. 1: PLL locked to required frequency 0: PLL not yet locked
30	PSO_DISABLE	R/W	0h	Disables the ability to switch off the analog switched power islands in the lane when in the ultra-low power state
29	PLL_PSO	R/W	0h	Power Shut Off signal for PLL 1: PLL shutoff 0: PLL power ON
28	PLL_PD	R/W	1h	Power down signal for PLL (Does not switch off the PLL supply) 1: PLL is powered down 0: PLL is active
27:26	RESERVED	NONE	0h	Reserved
25:16	PLL_FBDIV	R/W	FFh	DPHY TX PLL VCO Feedback Divider ratio. Feedback divider value = ROUND ((Data Rate * 2 * pll_opdiv * pll_ipdiv) / PLL reference clock frequency)
15:14	RESERVED	NONE	0h	Reserved
13:8	PLL_OPDIV	R/W	1h	DPHY TX PLL OUTCLK Divider ratio.<BR> 6'h01: Div by 1, 2.5 Gbps - 1.25 Gbps<BR> 6'h02: Div by 2, 1.24 Gbps - 630 Mbps<BR> 6'h04: Div by 4, 620 Mbps - 320 Mbps<BR> 6'h08: Div by 8, 310 Mbps - 160 Mbps<BR> 6'h10: Div by 16, 150 Mbps - 80 Mbps
7:5	RESERVED	NONE	0h	Reserved
4:0	PLL_IPDIV	R/W	1h	DPHY TX PLL REFCLK Input Divider ratio.<BR> 5'h01: Div by 1, 9.6 MHz - <19.2 MHz<BR> 5'h02: Div by 2, 19.2 MHz - <38.4 MHz<BR> 5'h04: Div by 4, 38.4 MHz - < 76.8 MHz<BR> 5'h08: Div by 8, 76.8 MHz - < 150 MHz