SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A0C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_RDLVL_GATE_CS_MAP | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_RDLVL_CS_MAP | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_RDLVL_GATE_ROTATE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | PI_RDLVL_GATE_CS_MAP | R/W | 0h | Defines the chip select map for gate training operations. Bit [0] controls cs0, bit [1] controls cs1, etc. Set each bit to 1 to enable chip for gate training. Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | PI_RDLVL_CS_MAP | R/W | 0h | Defines the chip select map for data eye training operations. Bit [0] controls cs0, bit [1] controls cs1, etc. Set each bit to 1 to enable chip for data eye training. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_RDLVL_GATE_ROTATE | R/W | 0h | Enables rotational CS for interval gate training. Set to 1 for rotating CS. Reset Source: ctl_amod_g_rst_n |