SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A010h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PI_TCMD_GAP | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PI_TCMD_GAP | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_NOTCARE_PHYUPD | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_INIT_LVL_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | PI_TCMD_GAP | R/W | 0h | Specifies the minimum gap in DFI clocks between two commands. Used to guard the timing from the last command of MC and the first command of PI when MC hand over the control of DFI to PI. Reset Source: ctl_amod_g_rst_n |
| 15:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | PI_NOTCARE_PHYUPD | R/W | 0h | Allow the PI to issue a controller request to the controller if a phyupd_req from the PHY has been detected.bit[1] represents supports in normal state;bit[0] represents supports in initialization state. Set to 1 to issue the controller request. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_INIT_LVL_EN | R/W | 0h | Enables the initial leveling sequence after PI initialization procedure. Set to 1 to enable. Reset Source: ctl_amod_g_rst_n |