SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A038h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_TMRR | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_SRX_LVL_TARGET_CS_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_RANK_NUM_PER_CKE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_CS_MASK | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PI_TMRR | R/W | 0h | DRAM tMRR value in memory clock cycles. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_SRX_LVL_TARGET_CS_EN | R/W | 0h | Defines self refresh exit trigger target rank/ranks training or all ranks training. 1: The rank/ranks exit from self refresh will trigger the corresponding rank/ranks training. Note: If multiple ranks exit from self refresh, current design only support the multiple ranks srx command issues at the same time. 0: Any rank/ranks exit from self refresh will trigger all ranks training Reset Source: ctl_amod_g_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | PI_RANK_NUM_PER_CKE | R/W | 0h | Defines the number of chip selects share one cke Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | PI_CS_MASK | R/W | 0h | Defines which chip selects are active. Reset Source: ctl_amod_g_rst_n |