SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Table 5-55 shows the boot parameter table for xSPI boot. Must be preceded with the common boot parameters described in Table 5-43.
| Byte Offset | Size (bytes) | Name | Default Value | Description |
|---|---|---|---|---|
| 256 | 1 | Port | 0 | Physical port number |
| 257 | 1 | Mode on | From Pins | If non-zero, the mode byte will be sent |
| 258 | 1 | Instruct Width | From Pins | Number of pins used to send instructions (1, 8) |
| 259 | 1 | Address Width | From Pins | Number of pins used to send address (1, 8) |
| 260 | 1 | Data Width | From Pins | Number of pins used to received data (1, 8) |
| 261 | 1 | Address Size | 24 | 24 and 32 bits are the valid address sizes |
| 262 | 1 | Mode | 0 | QSPI clock polarity and phase mode |
| 263 | 1 | CSEL | From Pins | Chip select number (0–3) |
| 264 | 1 | Read Cmd | From Pins | Command used to read read data |
| 265 | 1 | Mode byte | 0 | Value used for the mode byte (when active) |
| 266 | 1 | Dummy Cycles | From pins | Number of dummy cycles sent after the read command |
| 267 | 1 | clkRecovery | From pins | Clock recovery |
| 268 | 1 | dqsEnable | 0 | Enable DQS |
| 269 | 1 | ddrEnable | From pins | OSPI DDR mode operation |
| 270 | 2 | Module Freq | 0 | The QSPI module frequency after PLL enable, in kHz. If 0, ROM code uses the value from the module clock tables. |
| 272 | 4 | Bus Frequency | From pins | The QSPI bus frequency, in kHz |
| 276 | 4 | Delay | 0x08080808 or 0x01010101 | The chip select read delays. Default value is based on the read command |
| 280 | 1 | SFDP | From Pins | Enables SFDP parser for 1S-1S-1S to 8D-8D-8D switching |
| 284 | 4 | Tap Delay | 0xFFFFFFFF | The read tap selection. If 0xFFFFFFFF, the ROM code will scan the taps to find the best delay. The result will then overwrite the value in this table. |
| 288 | 1 | dtrCmdExt | 0 | BFPT Octal DTR Command Extension type: 00b - repeat, 01b - invert |
| 289 | 1 | dtrByteOrder | 0 | BFPT Octal DTR Byte Order: 0 - sequential, 1 - byte swapped |
| 290 | 1 | dtrDummyCycles | 8 | SFDP 8D # dummy cyles: 8 or 20 cycles |
| 292 | 4 | phyStatus | 0 | PHY Enabled/Disabled Status |
| 296 | 4 | Internal Clk | From pins | 0 = external (dqs) 1 = internal |
| 300 | 4 | inDAC | From pins | When 0, XIP mode is used |
| 304 | 4 | Read Index | 0 | Index to the active read address |
| 308 | 4 | Read Addr 0 | 0x000000 | The initial flash read address |
| 312 | 4 | Read Addr 1 | 0x400000 | Backup read address |