| csi_rx_if0 |
csi_rx_if0_corr_level_0 |
ESM0_esm_lvl_event_66 |
ESM0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_err_irq_0 |
ESM0_esm_lvl_event_0 |
ESM0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_err_irq_0 |
GICSS0_spi_175 |
GICSS0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_err_irq_0 |
WKUP_R5FSS0_CORE0_intr_170 |
WKUP_R5FSS0_CORE0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_err_irq_0 |
MCU_R5FSS0_CORE0_cpu0_intr_170 |
MCU_R5FSS0_CORE0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_fatal_0 |
ESM0_esm_lvl_event_70 |
ESM0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_irq_0 |
GICSS0_spi_173 |
GICSS0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_irq_0 |
WKUP_R5FSS0_CORE0_intr_173 |
WKUP_R5FSS0_CORE0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_irq_0 |
MCU_R5FSS0_CORE0_cpu0_intr_173 |
MCU_R5FSS0_CORE0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_level_0 |
ESM0_esm_lvl_event_72 |
ESM0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_level_0 |
GICSS0_spi_174 |
GICSS0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_level_0 |
WKUP_R5FSS0_CORE0_intr_174 |
WKUP_R5FSS0_CORE0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_level_0 |
MCU_R5FSS0_CORE0_cpu0_intr_174 |
MCU_R5FSS0_CORE0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_csi_nonfatal_0 |
ESM0_esm_lvl_event_71 |
ESM0 |
csi_rx_if0 interrupt request |
level |
| csi_rx_if0 |
csi_rx_if0_uncorr_level_0 |
ESM0_esm_lvl_event_77 |
ESM0 |
csi_rx_if0 interrupt request |
level |