SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Writing data at the GPMC_NAND_ADDRESS_i location (where i = 0 to 3) places the data as the NAND partial address value on the bus, using a regular asynchronous write access.
Figure 12-193 shows the NAND address latch cycle.
Figure 12-193 NAND Address Latch CycleALE is shared with the nADV output signal and has an inverted polarity from ADV. The NAND qualifier deals with this. During the asynchronous NAND data access cycle, ALE is kept stable.