SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A494h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_PREAMBLE_SUPPORT_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_WDQ_OSC_DELTA_INDEX_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_WDQ_OSC_DELTA_INDEX_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_WDQ_OSC_DELTA_INDEX_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | PI_PREAMBLE_SUPPORT_F0 | R/W | 0h | bit0: Selection of one or two cycle preamble for read burst transfers. bit1: Selection of one or two cycles write burst transfers for NON-DDR5,one or multi[up to four] cycles write burst transfers for DDR5. Reset Source: ctl_amod_g_rst_n |
| 23:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | PI_WDQ_OSC_DELTA_INDEX_F2 | R/W | 0h | WDQ DQS delay delta index for OSC triggered periodic training for frequency set 2. If the value is n, the delay is 2^n/512 cycle. Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | PI_WDQ_OSC_DELTA_INDEX_F1 | R/W | 0h | WDQ DQS delay delta index for OSC triggered periodic training for frequency set 1. If the value is n, the delay is 2^n/512 cycle. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | PI_WDQ_OSC_DELTA_INDEX_F0 | R/W | 0h | WDQ DQS delay delta index for OSC triggered periodic training for frequency set 0. If the value is n, the delay is 2^n/512 cycle. Reset Source: ctl_amod_g_rst_n |