SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A108h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PI_TDFI_INIT_COMPLETE_MIN | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_DRAM_CLK_DISABLE_DEASSERT_SEL | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PI_INIT_STARTORCOMPLETE_2_CLKDISABLE | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_CLKDISABLE_2_INIT_START | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | PI_TDFI_INIT_COMPLETE_MIN | R/W | 0h | Minimum number of DFI clocks from dfi_init_complete to a command/training event. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_DRAM_CLK_DISABLE_DEASSERT_SEL | R/W | 0h | Indicate dfi_dram_clk_disable deassert following dfi_init_start deassert or dfi_init_complete assert. Set to 0: dfi_dram_clk_disable deassert following dfi_init_start deassert. Set to 1: dfi_dram_clk_disable deassert following dfi_init_complete assert. Reset Source: ctl_amod_g_rst_n |
| 15:8 | PI_INIT_STARTORCOMPLETE_2_CLKDISABLE | R/W | 0h | Defines the delay from deasserting of dfi_init_start or asserting of dfi_init_complete to deasserting of dfi_dram_clk_disable in DFI clock. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PI_CLKDISABLE_2_INIT_START | R/W | 0h | Defines the delay from the asserting of dfi_dram_clk_disable to the asserting of dfi_init_start in DFI clock. Reset Source: ctl_amod_g_rst_n |