SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C070h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDQ_ENC_OBS_SELECT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_MASTER_DLY_LOCK_OBS_SELECT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_SW_FIFO_PTR_RST_DISABLE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_SLAVE_LOOP_CNT_UPDATE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | PHY_RDDQ_ENC_OBS_SELECT_0 | R/W | 0h | Select value to map the internal read DQ target delay encoded settings to the accessible read DQ encoded target delay observation register for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | PHY_MASTER_DLY_LOCK_OBS_SELECT_0 | R/W | 0h | Select value to map the internal controller delay observation registers to the accessible controller delay observation register for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PHY_SW_FIFO_PTR_RST_DISABLE_0 | R/W | 0h | Disables automatic reset of the read entry FIFO pointers for slice 0. Set to 1 to disable automatic resets. Reset Source: ctl_amod_g_rst_n |
| 7:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | PHY_SLAVE_LOOP_CNT_UPDATE_0 | R/W | 0h | Reserved for future use for slice 0. Reset Source: ctl_amod_g_rst_n |