SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C198h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_RESP_WAIT_CNT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_GTLVL_DLY_STEP_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_RESP_WAIT_CNT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:21 | RESERVED | NONE | 0h | Reserved |
| 20:16 | PHY_GTLVL_RESP_WAIT_CNT_0 | R/W | 0h | Number of cycles + 4 to wait between dfi_rddata_en and the sampling of the DQS during gate training for slice 0. The valid range is 0x0 to 0xB. Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | PHY_GTLVL_DLY_STEP_0 | R/W | 0h | DQS target delay step size during gate training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:6 | RESERVED | NONE | 0h | Reserved |
| 5:0 | PHY_WRLVL_RESP_WAIT_CNT_0 | R/W | 0h | Number of cycles to wait between dfi_wrlvl_strobe and the sampling of the DQs during write leveling for slice 0. Reset Source: ctl_amod_g_rst_n |