SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8468h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | FSP0_FRC | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | FSP1_FRC_VALID | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | FSP0_FRC_VALID | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FSP_WR_CURRENT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | FSP0_FRC | R/W | 0h | Identifies which of the controller's frequency copy is associated with FSP0. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | FSP1_FRC_VALID | R/W | 0h | Specifies whether the FSP set defined in the FSP1_FRC parameter reflects the frequency used to program the FSP1 registers. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | FSP0_FRC_VALID | R/W | 0h | Specifies whether the FSP set defined in the FSP0_FRC parameter reflects the frequency used to program the FSP0 registers. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | FSP_WR_CURRENT | R/W | 0h | Reports which FSP set the memory will target with write commands. Reset Source: ctl_amod_g_rst_n |