SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8464h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | FSP_OP_CURRENT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | FSP_STATUS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DFS_ALWAYS_WRITE_FSP | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FSP_PHY_UPDATE_MRW | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | FSP_OP_CURRENT | R/W | 0h | Reports which FSP set the memory is currently using. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | FSP_STATUS | R/W | 0h | Indicates that a DFS event caused the FSP mode registers to be updated. Value of 1 means that the FSP mode registers were changed. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | DFS_ALWAYS_WRITE_FSP | R/W | 0h | Forces all FSP mode registers to be written by the controller during a DFS event. Set to 1 to force the write. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | FSP_PHY_UPDATE_MRW | R/W | 0h | Identifies the logic responsible for updating MR12 and MR14 in memory. Clear to 0 for the controller, or set to 1 for the PHY or PI. Reset Source: ctl_amod_g_rst_n |