SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A12Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_WDQLVL_NEED_SAVE_RESTORE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_WDQLVL_ERROR_STATUS | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_WDQLVL_DISABLE_DFS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PI_WDQLVL_NEED_SAVE_RESTORE | R/W | 0h | Enables the use of functional DRAM address space for write DQ training, 1 = enable, not for LPDDR4. Reset Source: ctl_amod_g_rst_n |
| 15:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | PI_WDQLVL_ERROR_STATUS | R | 0h | Holds the error associated with the write dq level error interrupt. Bit [0] set indicates a PI_TDFI_WDQLVL_MAX parameter violation and bit [1] set indicates a PI_TDFI_WDQLVL_RESP parameter violation. READ-ONLY. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_WDQLVL_DISABLE_DFS | R/W | 0h | Disable automatic write DQ training on freq change. Set to 1 to disable. Reset Source: ctl_amod_g_rst_n |