SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A314h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_TODTON_MIN_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_ODTLON_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_ODT_EN_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_TODTL_2CMD_F2 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PI_TODTON_MIN_F0 | R/W | 0h | Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 0. Reset Source: ctl_amod_g_rst_n |
| 23:20 | RESERVED | NONE | 0h | Reserved |
| 19:16 | PI_ODTLON_F0 | R/W | 0h | Defines the latency from a CAS-2 command to the tODTon reference for frequency set 0. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PI_ODT_EN_F2 | R/W | 0h | Enable support of DRAM ODT. When enabled, PI will assert and de-assert ODT output to DRAM as needed for frequency set 2. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PI_TODTL_2CMD_F2 | R/W | 0h | Defines the DRAM delay from an ODT de-assertion to the next non-write, non-read command for frequency set 2. Reset Source: ctl_amod_g_rst_n |