SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 86A4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | TDFI_DRAM_CLK_DISABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TDFI_CTRLUPD_MIN | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TDFI_CTRLUPD_MIN | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DRAM_CLK_DISABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | TDFI_DRAM_CLK_DISABLE | R/W | 0h | Defines the DFI tDRAM_CLK_DISABLE timing parameter [in DFI clocks], the delay between a dfi_dram_clock_disable assertion and the memory clock disable. Reset Source: ctl_amod_g_rst_n |
| 23:8 | TDFI_CTRLUPD_MIN | R/W | 0h | Defines the DFI tCTRLUPD_MIN timing parameter [in DFI clocks], the minimum cycles that dfi_ctrlupd_req must be asserted. Reset Source: ctl_amod_g_rst_n |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | DRAM_CLK_DISABLE | R/W | 0h | Set value for the dfi_dram_clk_disable signal. Bit [0] controls cs0, bit [1] controls cs1, etc. Set each bit to 1 to disable. Reset Source: ctl_amod_g_rst_n |