SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C088h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_PATT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_BURST_CNT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18:16 | PHY_WDQLVL_PATT_0 | R/W | 0h | Defines the training patterns to be used during the write data leveling sequence for slice 0. Bit [0] corresponds to the LFSR data training pattern. Bit [1] corresponds to the CLK data training pattern. Bit [2] corresponds to user-defined data pattern training. If multiple bits are set, the training for each of the chosen patterns will be executed and the settings that give the smallest data valid window eye will be chosen. Reset Source: ctl_amod_g_rst_n |
| 15:14 | RESERVED | NONE | 0h | Reserved |
| 13:8 | PHY_WDQLVL_BURST_CNT_0 | R/W | 0h | Defines the write/read burst length in bytes during the write data leveling sequence for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PHY_WDQLVL_CLK_JITTER_TOLERANCE_0 | R/W | 0h | Defines the minimum gap requirment for the LE and TE window for slice 0. Reset Source: ctl_amod_g_rst_n |