SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8630h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TDFI_PHY_RDLAT_F0 | |||||||
| R/W | |||||||
| 6h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | MEM_RST_VALID | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | CKE_STATUS | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | AXI0_W_PRIORITY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | TDFI_PHY_RDLAT_F0 | R/W | 6h | Defines the DFI tPHY_RDLAT timing parameter [in DFI PHY clocks], the maximum cycles between a dfi_rddata_en assertion and a dfi_rddata_valid assertion. FC=0 Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | MEM_RST_VALID | R | 0h | Register access to mem_rst_valid signal. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | CKE_STATUS | R | 0h | Register access to cke_status signal. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | AXI0_W_PRIORITY | R/W | 0h | Priority of write commands from AXI port 0. 0 is the highest priority. This may only be changed before initialization begins or when the controller is quiescent, there is no data in the port FIFOs, and the AXI0_FIXED_PORT_PRIORITY_ENABLE parameter is low. Reset Source: ctl_amod_g_rst_n |