SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C1B4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DATA_DC_WDQLVL_ENABLE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_DATA_DC_WRLVL_ENABLE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 | R/W | 0h | Clock measurement cell threshold offset for differential signals for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:16 | PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 | R/W | 0h | Clock measurement cell threshold offset for single ended signals for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PHY_DATA_DC_WDQLVL_ENABLE_0 | R/W | 0h | Enable duty cycle adjust during write DQ training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PHY_DATA_DC_WRLVL_ENABLE_0 | R/W | 0h | Enable duty cycle adjust during write leveling for slice 0. Reset Source: ctl_amod_g_rst_n |