SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Return to Summary Table
| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C07Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GTLVL_UPDT_WAIT_CNT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_GTLVL_CAPTURE_CNT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_MASK_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WRLVL_UPDT_WAIT_CNT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PHY_GTLVL_UPDT_WAIT_CNT_0 | R/W | 0h | Number of cycles + 4 to wait after changing DQS target delay setting during gate training for slice 0. The valid range is 0x0 to 0xB. Reset Source: ctl_amod_g_rst_n |
| 23:22 | RESERVED | NONE | 0h | Reserved |
| 21:16 | PHY_GTLVL_CAPTURE_CNT_0 | R/W | 0h | Number of samples to take at each DQS target delay setting during gate training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:8 | PHY_DQ_MASK_0 | R/W | 0h | For ECC slice, should set this register to do DQ bit mask for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | PHY_WRLVL_UPDT_WAIT_CNT_0 | R/W | 0h | Number of cycles to wait after changing DQS target delay setting during write leveling for slice 0. Reset Source: ctl_amod_g_rst_n |