SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
This device supports an Arm® CoreSight™ compliant four-channel programmable on-chip Cross Triggering network. In addition to the four-channel on-chip network, this device implements two channels of product level triggering via the EMU0 and EMU1 device pins.
Conceptually, each channel of Cross Triggering can be viewed as mapping of a user-defined set of events to a user-defined set of actions, where the occurrence of any event in the set-of-events results in the generation of the set-of-actions. Table 13-9 provides a domain-level summary of the supported events and actions.
| Domain | Events | Actions |
|---|---|---|
| Product-Level | Zero detected on EMU0 input pin | EMU0 output pin driven to Zero |
| Zero detected on EMU1 input pin | EMU1 output pin driven to Zero | |
| SoC Debug | TBR Acquisition Complete | TPIU insert trigger packet |
| TBR Embedded buffer is full | TPIU start flush process | |
| System reset asserted | TBR insert trigger packet | |
| Bus Probe-n match | TBR start flush process | |
| STM write to a TRIG location | Bus Probe-n Start | |
| STM write to a trigger-enabled stimulus port | Bus Probe-n Stop | |
| MCU_R5F | MCU_R5F has halted | MCU_R5F - halt request |
| PMU generated interrupt | MCU_R5F - resume request | |
| ETM External Out (EXTOUT) trigger | ETM External In (EXTIN) trigger | |
| WKUP_R5F | WKUP_R5F has halted | WKUP_R5F – halt request |
| PMU generated interrupt | WKUP_R5F – resume request | |
| ETM External Out (EXTOUT) trigger | ETM External In (EXTIN) trigger | |
| A53SS0 | A53SS0 core-n has halted | A53SS0 core-n – halt request |
| PMU generated interrupt | A53SS0 core-n – resume request | |
| ETM generated trigger | CTI interrupt | |
| -- | ETM External In (EXTIN) trigger |