SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 84F8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | ZQ_SW_REQ_START_LATCH_MAP | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | TZQLAT_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | TZQCAL_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TZQCAL_F2 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | ZQ_SW_REQ_START_LATCH_MAP | R/W | 0h | Specifies which chip selects will simultaneously receive a ZQ start or latch command once the ZQ_REQ parameter is written with a ZQ Start or ZQ Latch command. Reset Source: ctl_amod_g_rst_n |
| 23 | RESERVED | NONE | 0h | Reserved |
| 22:16 | TZQLAT_F2 | R/W | 0h | Holds the DRAM ZQLAT value in cycles. FC=2 Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:0 | TZQCAL_F2 | R/W | 0h | Holds the DRAM ZQCAL value in cycles. FC=2 Reset Source: ctl_amod_g_rst_n |