SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C040h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_GATE_SMPL2_SLAVE_DELAY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_GATE_SMPL2_SLAVE_DELAY_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_MEM_CLASS_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LPDDR_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24:16 | PHY_GATE_SMPL2_SLAVE_DELAY_0 | R/W | 0h | Number of cycles to delay the read DQS gate signal to generate gate2 signal for on-the-fly read DQS training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:11 | RESERVED | NONE | 0h | Reserved |
| 10:8 | PHY_MEM_CLASS_0 | R/W | 0h | Indicates the type of DRAM for slice 0. 0 for DDR3, 1 for DDR4, 2 for DDR5, 4 for LPDDR2, 5 for LPDDR3. 6 for LPDDR4 Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PHY_LPDDR_0 | R/W | 0h | Adds a cycle of delay for the slice 0 to match the address slice. Set to 1 to add a cycle Reset Source: ctl_amod_g_rst_n |