SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 846Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | ADDR_SPACE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | BIST_RESULT | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | BIST_GO | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FSP1_FRC | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED | NONE | 0h | Reserved |
| 29:24 | ADDR_SPACE | R/W | 0h | Sets the number of address bits to check during BIST operation. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | BIST_RESULT | R | 0h | BIST operation status [pass/fail]. Bit [0] indicates data check status and bit [1] indicates address check status. Value of 1 is a passing result. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | BIST_GO | W | 0h | Initiate a BIST operation. Set to 1 to trigger. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | FSP1_FRC | R/W | 0h | Identifies which of the controller's frequency copy is associated with FSP1. Reset Source: ctl_amod_g_rst_n |