SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C188h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_RDDATA_EN_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WDQLVL_IE_ON_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DBI_MODE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_IE_MODE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | PHY_WDQLVL_RDDATA_EN_DLY_0 | R/W | 0h | For WR DQ training, the number of cycles that the dfi_rddata_en signal is early for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PHY_WDQLVL_IE_ON_0 | R/W | 0h | IE control, 1 meams IE is always on during WR DQ training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:10 | RESERVED | NONE | 0h | Reserved |
| 9:8 | PHY_DBI_MODE_0 | R/W | 0h | DBI mode for slice 0. Bit [0] enables return of DBI read data. Reset Source: ctl_amod_g_rst_n |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | PHY_IE_MODE_0 | R/W | 0h | Input enable mode bits for slice 0. Bit [0] enables the mode where the input enables are always on; set to 1 to enable. Bit [1] disables the input enable on the DM signal; set to 1 to disable. Reset Source: ctl_amod_g_rst_n |