SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A014h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_DFI_PHYMSTR_TYPE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_DFI_VERSION | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_TRAIN_ALL_FREQ_REQ | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_RESERVED0 | |||||||
| R/W | |||||||
| 64h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | PI_DFI_PHYMSTR_TYPE | R/W | 0h | DFI Controller Request Type used for dfi 4.1 verision: This signal indicates the required state of DRAM when PHY becomes the controller. Each memory rank uses one bit. 1'b0: IDLE. The MC should close all the pages. 1'b1: IDLE or Self Refresh. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_DFI_VERSION | R/W | 0h | Define the DFI controller version, set 1 for DFI4.1, set 0 for DFI4.0 Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PI_TRAIN_ALL_FREQ_REQ | W | 0h | Triggers training for all supported frequencies in PI_FREQ_MAP. Applies to LPDDR4 devices onlyh. Set to 1 to trigger. Only applicable after memory initialization has been completed. Can be used to train new frequencies that were not available at initialization time. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:0 | PI_RESERVED0 | R/W | 64h | Reserved |