SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A264h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_RESERVED27 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_MRW_STATUS | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PI_RESERVED27 | R/W | 0h | Reserved |
| 7:0 | PI_MRW_STATUS | R | 0h | Write memory mode register status. Bit [0] set indicates a WRITE_MODEREG parameter programming error. Bit [1] set indicates a PASR error. Bit [2] is Reserved. Bit [3] set indicates a self refresh or deep power down error. Bit [4] set indicates that a write to MR3 or MR11 was attempted [write_modereg bit [25] was asserted with bit [17] set, or bit [23] was asserted with bits [7:0] defining MR3 or MR11] during tZQCAL after a ZQ calibration start command. READ-ONLY Reset Source: ctl_amod_g_rst_n |