SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A110h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_WDQLVL_RESP_MASK | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_WDQLVL_BST_NUM | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_WDQLVL_VREF_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_INIT_COMPLETE_TO_MC_DELAY_COUNT | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PI_WDQLVL_RESP_MASK | R/W | 0h | Write DQ training response mask. When set to 1, the dfi_wdqlvl_en of the slice is not asserted. Reset Source: ctl_amod_g_rst_n |
| 23:19 | RESERVED | NONE | 0h | Reserved |
| 18:16 | PI_WDQLVL_BST_NUM | R/W | 0h | Defines the number of write/read bursts issued at each step in write DQ training. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PI_WDQLVL_VREF_EN | R/W | 0h | Control for VREF training as part of non-initialization write DQ training. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PI_INIT_COMPLETE_TO_MC_DELAY_COUNT | R/W | 0h | It controls the time PI bypass CKE at the beginning of PI mask dfi_init_complete to controller. Reset Source: ctl_amod_g_rst_n |