SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C18Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_SW_MASTER_MODE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_RDDATA_EN_OE_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_RDDATA_EN_TSEL_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PHY_SW_MASTER_MODE_0 | R/W | 0h | Controller delay line override settings for slice 0. Bit [0] enables software half clock mode. Bit [1] is the software half clock mode value. Bit [2] enables software bypass mode. Bit [3] is the software bypass mode value. Reset Source: ctl_amod_g_rst_n |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20:16 | PHY_RDDATA_EN_OE_DLY_0 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for LP4 OE extension generation for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | PHY_RDDATA_EN_TSEL_DLY_0 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:5 | RESERVED | NONE | 0h | Reserved |
| 4:0 | PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0 | R/W | 0h | For WR DQ training, the number of cycles that the dfi_rddata_en signal is earlier than necessary for TSEL enable generation for slice 0. Reset Source: ctl_amod_g_rst_n |