SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A2C0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PI_TVREF_F0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PI_TVREF_F0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_PHYMSTR_REQ_ACK_LOOP_DELAY | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_NOTCARE_MC_INIT_START | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | PI_TVREF_F0 | R/W | 0h | Defines the number of cycles that the PI should wait before issuing the next command after a VREF training MRW command for frequency set 0. Reset Source: ctl_amod_g_rst_n |
| 15:11 | RESERVED | NONE | 0h | Reserved |
| 10:8 | PI_PHYMSTR_REQ_ACK_LOOP_DELAY | R/W | 0h | The delay between phymstr_req and inner phymstr_ack when PI_DISABLE_PHYMSTR_REQ set 1 Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_NOTCARE_MC_INIT_START | R/W | 0h | Defines whether PI waits for the controller to initiate dfi_init_start before PI memory initialization, 1: wait for dfi_init_start Reset Source: ctl_amod_g_rst_n |