SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A20Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_BIST_PAT_MODE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_BIST_ADDR_MODE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_BIST_MODE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_BIST_ADDR_MASK_9_1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | PI_BIST_PAT_MODE | R/W | 0h | Sets the pattern mode of BIST. 'b00 indicates using built-in pattern. 'b01 indicates checkerboard pattern, each data transfer inverts the last data transfer based on the built-in pattern. 'b10 indicates using both user pattern and built-in pattern. 'b11 indicates using pi lfsr random pattern. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PI_BIST_ADDR_MODE | R/W | 0h | Sets the address traversing order of BIST. 'b00 indicates fast column order [burst-column-bank-row-rank]. 'b01 indicates fast row order [burst-row-column-bank-rank]. 'b10 indicates fast bank order [burst-bank-column-row-rank]. Reset Source: ctl_amod_g_rst_n |
| 15:11 | RESERVED | NONE | 0h | Reserved |
| 10:8 | PI_BIST_MODE | R/W | 0h | Sets the BIST data checking mode. 'b00 indicates MOVI13N mode. 'b01 indicates March C mode. 'b10 indicates GALPAT mode. 'b11 indicates PRBS mode. 'b100 indicates programmable March data check mode. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | PI_BIST_ADDR_MASK_9_1 | R/W | 0h | Defines an address to be masked during the BIST operation.. Reset Source: ctl_amod_g_rst_n |