SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C030h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_PRBS_PATTERN_START_0 | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_PDA_MODE_EN_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_DQ_IDLE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_IDLE_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | RESERVED | NONE | 0h | Reserved |
| 30:24 | PHY_PRBS_PATTERN_START_0 | R/W | 1h | PRBS7 start pattern for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PHY_PDA_MODE_EN_0 | R/W | 0h | When set to 1, the invalid DQs will be driven by the dfi_wrdata to make sure the tpda_s and tpda_h's timing is meet for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8:0 | PHY_DQ_IDLE_0 | R/W | 0h | When set to 1, the inavlid DQ will be driven to high, when set to 0, the invalid DQ will be driven to low for slice 0. Reset Source: ctl_amod_g_rst_n |