SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A2B8h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_CATR | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_PARALLEL_CALVL_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_RESERVED53 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_FREQ_SEL_FROM_REGIF | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:28 | RESERVED | NONE | 0h | Reserved |
| 27:24 | PI_CATR | R/W | 0h | It indicates LP4 DRAM CA terminition ON/OFF state. Each bit corresponds to each chip select. 1:ON 0:OFF. This parameter is active when PI_NO_CATR_READ==1. When PI_NO_CATR_READ==0, this param is inactive Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_PARALLEL_CALVL_EN | R/W | 0h | Enable parallel channel CA training for LPDDR4. 1: All the channels in one rank do CA Training in parallel. 0: Each channel does CA Training in sequence Reset Source: ctl_amod_g_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | PI_RESERVED53 | R/W | 0h | Reserved |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PI_FREQ_SEL_FROM_REGIF | R/W | 0h | In non-DFI 4.0 mode, user select the frequency copies from pi_freq_change_reg_copy. Reset Source: ctl_amod_g_rst_n |