SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C078h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WRLVL_CAPTURE_CNT_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_WRLVL_ALGO_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | SC_PHY_LVL_DEBUG_CONT_0 | ||||||
| NONE | W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LVL_DEBUG_MODE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED | NONE | 0h | Reserved |
| 29:24 | PHY_WRLVL_CAPTURE_CNT_0 | R/W | 0h | Number of samples to take at each DQS target delay setting during write leveling for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PHY_WRLVL_ALGO_0 | R/W | 0h | Write leveling algorithm selection for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | SC_PHY_LVL_DEBUG_CONT_0 | W | 0h | Allows the leveling state machine to advance [when in debug mode] for slice 0. Set to 1 to trigger. WRITE-ONLY Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PHY_LVL_DEBUG_MODE_0 | R/W | 0h | Enables leveling debug mode for slice 0. Set to 1 to enable. Reset Source: ctl_amod_g_rst_n |