SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C0F0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_DQDM_TE_DLY_OBS_0 | ||||||
| NONE | R | ||||||
| 0h | 7FFh | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WDQLVL_DQDM_TE_DLY_OBS_0 | |||||||
| R | |||||||
| 7FFh | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_DQDM_LE_DLY_OBS_0 | ||||||
| NONE | R | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DQDM_LE_DLY_OBS_0 | |||||||
| R | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RESERVED | NONE | 0h | Reserved |
| 26:16 | PHY_WDQLVL_DQDM_TE_DLY_OBS_0 | R | 7FFh | Observation register containing write data leveling data window trailing edge target delay setting for slice 0. READ-ONLY Reset Source: ctl_amod_g_rst_n |
| 15:11 | RESERVED | NONE | 0h | Reserved |
| 10:0 | PHY_WDQLVL_DQDM_LE_DLY_OBS_0 | R | 0h | Observation register containing write data leveling data window leading edge target delay setting for slice 0. READ-ONLY Reset Source: ctl_amod_g_rst_n |