SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8604h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | EN_ODT_ASSERT_EXCEPT_RD | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | ODT_EN_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ODT_EN_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | ODT_EN_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | EN_ODT_ASSERT_EXCEPT_RD | R/W | 0h | Enable controller to assert ODT at all times except during reads. Assumes single ODT pin connected. Set to 1 to enable. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | ODT_EN_F2 | R/W | 0h | Enable support of DRAM ODT. When enabled, controller will assert and de-assert ODT output to DRAM as needed. FC=2 Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | ODT_EN_F1 | R/W | 0h | Enable support of DRAM ODT. When enabled, controller will assert and de-assert ODT output to DRAM as needed. FC=1 Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | ODT_EN_F0 | R/W | 0h | Enable support of DRAM ODT. When enabled, controller will assert and de-assert ODT output to DRAM as needed. FC=0 Reset Source: ctl_amod_g_rst_n |