SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C01Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_LP4_BOOT_RPTR_UPDATE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles that the dfi_rddata_en signal is earlier than necessary for extended OE generation for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:18 | RESERVED | NONE | 0h | Reserved |
| 17:16 | PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0 | R/W | 0h | For LPDDR4 boot frequency, write path clock gating disable for slice 0. Bit [0]: disable pull in wrdata_en; Bit [1]: disable write path clock gating, clock always on Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0 | R/W | 0h | For LPDDR4 boot frequency, the number of cycles to delay the incoming dfi_rddata_en for read DQS gate generation for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | PHY_LP4_BOOT_RPTR_UPDATE_0 | R/W | 0h | For LPDDR4 boot frequency, the offset in cycles from the dfi_rddata_en signal to releasing data from the entry FIFO for slice 0. Reset Source: ctl_amod_g_rst_n |