SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C184h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_RDDATA_EN_IE_DLY_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQS_IE_TIMING_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_IE_TIMING_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PHY_PER_CS_TRAINING_EN_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | PHY_RDDATA_EN_IE_DLY_0 | R/W | 0h | Number of cycles that the dfi_rddata_en signal is earlier than necessary for input enable generation for slice 0. Reset Source: ctl_amod_g_rst_n |
| 23:16 | PHY_DQS_IE_TIMING_0 | R/W | 0h | Start/end timing values for DQS input enable signals for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:8 | PHY_DQ_IE_TIMING_0 | R/W | 0h | Start/end timing values for DQ/DM input enable signals for slice 0. Reset Source: ctl_amod_g_rst_n |
| 7:1 | RESERVED | NONE | 0h | Reserved |
| 0 | PHY_PER_CS_TRAINING_EN_0 | R/W | 0h | Enables the per-rank training and read/write timing capabilities for slice 0. Must have same value in all slices. Reset Source: ctl_amod_g_rst_n |