SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
The following are the PLLs in the device in MAIN domain:
Overview of the device PLLs with their reference clock options in MAIN domain is shown on Figure 6-42. For more specific information about PLLs see Section 6.4.5.5, PLLs Device-Specific Information.
The external muxes of choosing the reference clocks are glitch-free muxes.