SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A10Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_MC_DFS_PI_SET_VREF_ENABLE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_VREFLVL_DISABLE_DFS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_VREF_PDA_EN | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | PI_VREF_CS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | PI_MC_DFS_PI_SET_VREF_ENABLE | R/W | 0h | Enable the PI to set VREF value after DFS issued by MC. MR12 and MR14 for LPDDR4. MR6 for DDR4. 1 means disable. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | PI_VREFLVL_DISABLE_DFS | R/W | 0h | Disables automatic VREF training on freq change. Set to 1 to disable. Reset Source: ctl_amod_g_rst_n |
| 15:9 | RESERVED | NONE | 0h | Reserved |
| 8 | PI_VREF_PDA_EN | R/W | 0h | Enable per-DRAM addressability during VREF training. Set to 1 to enable. Reset Source: ctl_amod_g_rst_n |
| 7:2 | RESERVED | NONE | 0h | Reserved |
| 1:0 | PI_VREF_CS | R/W | 0h | Specifies the target chip select for the VREF training operation. Reset Source: ctl_amod_g_rst_n |