SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 A104h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PI_REFRESH_BETWEEN_SEGMENT_DISABLE | ||||||
| NONE | R/W | ||||||
| 0h | 1h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | PI_SW_CA_TRAIN_VREF | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PI_CALVL_STROBE_NUM | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PI_TCKCKEH | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24 | PI_REFRESH_BETWEEN_SEGMENT_DISABLE | R/W | 1h | Disable the refresh between CA first and second segment training. Set to 1 to disable. Reset Source: ctl_amod_g_rst_n |
| 23 | RESERVED | NONE | 0h | Reserved |
| 22:16 | PI_SW_CA_TRAIN_VREF | R/W | 0h | The Vref value which is set for SW step by step CA training. Reset Source: ctl_amod_g_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | PI_CALVL_STROBE_NUM | R/W | 0h | The consecutive dfi_calvl_strobe number when updating the CA vref data. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PI_TCKCKEH | R/W | 0h | DRAM tCKELCK Clock and command valid before CKE HIGH. Reset Source: ctl_amod_g_rst_n |