SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
Counter Timer IRQENABLE_CLR Register. This register is to disable generation of Interrupt Event used by SW. This register exists only if NUMTIMR > 0
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS0 | 0007 3C02 2C10h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| TIM_INTN_IEC | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| TIM_INTN_IEC | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TIM_INTN_IEC | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TIM_INTN_IEC | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | TIM_INTN_IEC | R/W | 0h | IRQCLR value. This bit clears the enable of the interrupt event. SW can also read this bit to determine if the interrupt is enabled. The individual bits is this field correspond to individual interrupts generated for each timer associated with Counter Timer Control Register (CTCRn : INT). |