SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C1BCh |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PHY_DQ_DM_SWIZZLE0_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_DQ_DM_SWIZZLE0_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| PHY_DQ_DM_SWIZZLE0_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_DQ_DM_SWIZZLE0_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:0 | PHY_DQ_DM_SWIZZLE0_0 | R/W | 0h | DQ/DM bit swizzling 0 for slice 0. Bits [3:0] inform the PHY which bit in {DM,DQ]} map to DQ0, Bits [7:4] inform the PHY which bit in {DM,DQ} map to DQ1, etc. Reset Source: ctl_amod_g_rst_n |