SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| WKUP_CTRL_MMR0 | 4300 C2C4h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| POST_CFG_FAST_POST_EN | POST_CFG_POST_DIV2 | RESERVED | POST_CFG_POST_DIV1 | ||||
| R | R | NONE | R | ||||
| X | X | 0h | X | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | POST_CFG_REF_DIV | ||||||
| NONE | R | ||||||
| 0h | X | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | POST_CFG_FB_DIV_INT | ||||||
| NONE | R | ||||||
| 0h | X | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| POST_CFG_FB_DIV_INT | |||||||
| R | |||||||
| X | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | POST_CFG_FAST_POST_EN | R | X | Activate Fast POST mode Field values (others are reserved): 1'b0 - DEACTIVATE 1'b1 - ACTIVATE Reset Source: mod_por_rst_n |
| 30:28 | POST_CFG_POST_DIV2 | R | X | Fast POST PLL secondary post-divider value, must be less than or equal to post_div1. Field values (others are reserved): 3'b000 - UNSUPPORTED 3'b001 - DIV1 3'b010 - DIV2 3'b011 - DIV3 3'b100 - DIV4 3'b101 - DIV5 3'b110 - DIV6 3'b111 - DIV7 Reset Source: mod_por_rst_n |
| 27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | POST_CFG_POST_DIV1 | R | X | Fast POST PLL primary post-divider value, must be greater than or equal to post_div2. Field values (others are reserved): 3'b000 - UNSUPPORTED 3'b001 - DIV1 3'b010 - DIV2 3'b011 - DIV3 3'b100 - DIV4 3'b101 - DIV5 3'b110 - DIV6 3'b111 - DIV7 Reset Source: mod_por_rst_n |
| 23:22 | RESERVED | NONE | 0h | Reserved |
| 21:16 | POST_CFG_REF_DIV | R | X | Fast POST PLL reference clock pre-divider value. Field values (others are reserved): 6'b000000 - UNSUPPORTED 6'b000001 - DIV1 6'b000010 - DIV2 6'b000011 - DIV3 6'b000100 - DIV4 6'b000101 - DIV5 6'b000110 - DIV6 6'b000111 - DIV7 6'b001000 - DIV8 6'b001001 - DIV9 6'b001010 - DIV10 6'b001011 - DIV11 6'b001100 - DIV12 6'b001101 - DIV13 6'b001110 - DIV14 6'b001111 - DIV15 6'b010000 - DIV16 6'b010001 - DIV17 6'b010010 - DIV18 6'b010011 - DIV19 6'b010100 - DIV20 6'b010101 - DIV21 6'b010110 - DIV22 6'b010111 - DIV23 6'b011000 - DIV24 6'b011001 - DIV25 6'b011010 - DIV26 6'b011011 - DIV27 6'b011100 - DIV28 6'b011101 - DIV29 6'b011110 - DIV30 6'b011111 - DIV31 6'b100000 - DIV32 6'b100001 - DIV33 6'b100010 - DIV34 6'b100011 - DIV35 6'b100100 - DIV36 6'b100101 - DIV37 6'b100110 - DIV38 6'b100111 - DIV39 6'b101000 - DIV40 6'b101001 - DIV41 6'b101010 - DIV42 6'b101011 - DIV43 6'b101100 - DIV44 6'b101101 - DIV45 6'b101110 - DIV46 6'b101111 - DIV47 6'b110000 - DIV48 6'b110001 - DIV49 6'b110010 - DIV50 6'b110011 - DIV51 6'b110100 - DIV52 6'b110101 - DIV53 6'b110110 - DIV54 6'b110111 - DIV55 6'b111000 - DIV56 6'b111001 - DIV57 6'b111010 - DIV58 6'b111011 - DIV59 6'b111100 - DIV60 6'b111101 - DIV61 6'b111110 - DIV62 6'b111111 - DIV63 Reset Source: mod_por_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:0 | POST_CFG_FB_DIV_INT | R | X | Fast POST PLL feedback divider (integer portion) value. In Integer mode values of 16 - 3200 (decimal) are supported. Reset Source: mod_por_rst_n |