SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 C1A0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | PHY_WDQLVL_DM_SEARCH_RANGE_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| PHY_WDQLVL_DM_SEARCH_RANGE_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | PHY_WDQLVL_QTR_DLY_STEP_0 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PHY_WDQLVL_DLY_STEP_0 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:25 | RESERVED | NONE | 0h | Reserved |
| 24:16 | PHY_WDQLVL_DM_SEARCH_RANGE_0 | R/W | 0h | The dm target delay search range for non-lpddr4 DM training for slice 0. Reset Source: ctl_amod_g_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | PHY_WDQLVL_QTR_DLY_STEP_0 | R/W | 0h | Defines the step granularity for the logic to use once an edge is found for slice 0. When this occurs, the logic jumps back to the previous invalid value and uses this step size to determine a more accurate delay value. Reset Source: ctl_amod_g_rst_n |
| 7:0 | PHY_WDQLVL_DLY_STEP_0 | R/W | 0h | DQ target delay step size during write data leveling for slice 0. Reset Source: ctl_amod_g_rst_n |