SPRUJ83D December 2023 – January 2026 AM62P , AM62P-Q1
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| Instance Name | Physical Address |
|---|---|
| DDR32SS0 | 0F30 8540h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | WR_ORDER_REQ | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | IN_ORDER_ACCEPT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | Q_FULLNESS | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DEVICE3_BYTE0_CS1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:26 | RESERVED | NONE | 0h | Reserved |
| 25:24 | WR_ORDER_REQ | R/W | 0h | Determines if the controller can re-order write commands from the same source ID and/or the same port. Bit [0] controls source ID usage and bit [1] controls port ID usage. Set each bit to 1 to enable usage in placement logic. Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | IN_ORDER_ACCEPT | R/W | 0h | Forces the controller to accept commands in the order in which they are placed in the command queue. Reset Source: ctl_amod_g_rst_n |
| 15:13 | RESERVED | NONE | 0h | Reserved |
| 12:8 | Q_FULLNESS | R/W | 0h | Quantity that determines when the command queue almost full signal will assert [q_almost_full]. When cleared to 0, the q_almost_full signal will be driven to 0 irrespective of number of entries in the command queue. Reset Source: ctl_amod_g_rst_n |
| 7:4 | RESERVED | NONE | 0h | Reserved |
| 3:0 | DEVICE3_BYTE0_CS1 | R/W | 0h | Defines the byte location of byte0 in the memory datapath for device 3 on chip 1. Used for MRRs to identify where data will be returned. DEV=3 Reset Source: ctl_amod_g_rst_n |